Technical Field
The present disclosure relates to a start-stop synchronous type serial data acquisition device and a start-stop synchronous type serial data acquisition method.
Related Art
In start-stop synchronous type serial communication, control signal lines for always synchronizing serial data, such as signal lines that transmit clock signal, do not exist. Accordingly, in start-stop synchronous type serial communication, communications are performed by generating a baud rate based on a clock signal for communication that is used within respective communication circuits. However, difference arises in the baud rates generated in respective signal circuits, and the differences in the baud rates become differences in acquisition timings of serial data.
In a conventional start-stop synchronous type serial communication, as illustrated in FIG. 7 as an example, received data is sampled at the rising edge of the baud rate (at a fixed timing) that is generated in a reception circuit. Further, the differences in baud rate between each of the communication circuits are corrected by adjusting high level segments of the baud rate generated in the reception circuit, in a case in which stop bit has been detected.
Further, as technology for suppressing the baud rate differences, Japanese Patent Application Laid-open (JP-A) No. 2000-216834 discloses a synchronizing circuit that controls output of synchronizing clock signal that synchronize the received data. In this synchronization circuit, starting positions of the received data are detected at the rising edges and falling edges of a detection clock signal, and the synchronization clock signal is output based on the rising edge or falling edge that is closest to the detected starting position.
In a case in which a low speed clock signal having an order of several tens of kHz is used for sampling, detection of start bit may delay for one cycle in maximum, depending on the timing of the input of the start bit, as illustrated in FIG. 9 as an example (a 38.4 kHz clock signal is illustrated in FIG. 9 as the example).
On the other hand, in the technology described in JP-A No. 2000-216834, since a circuit that operates based on the rising edges and a circuit that operates based on the falling edges are required, circuit scale of a counter that generates the baud rate may be doubled.
Further, as technology for suppressing a delay in the acquisition timing of serial data, there is a sampling method that dynamically switches all of operating clock signal edges based on the edge that has detected the start bit. However, this method is not recommended for use in synchronizing designs employing register transfer level (RTL) (for example, a design based on that the data is acquired at the rise of the clock signal), which is currently in mainstream usage, or in static timing analysis (STA) which is based on a synchronizing design. Further, in the above method, high difficulty in design and high verification may be necessary.